In a Dt-MOS transistor, a gate electrode is short-circuited to a semiconductor layer or a well region where a channel region is formed, and an input signal is applied at the same time to both the gate electrode and the semiconductor layer or the well region where the channel region is formed. This configuration makes it possible to achieve a low off-state current and a high on-state current with a low threshold voltage and thereby makes it possible to reduce the power consumption. The semiconductor layer or the well region where the channel region is formed may be called a body.
FIG. 1 is a drawing illustrating an exemplary configuration of a typical Dt-MOS transistor 10, and FIG. 2 is a graph representing operating characteristics of the Dt-MOS transistor 10 of FIG. 1.
The Dt-MOS transistor 10 of FIG. 1 is an n-channel MOS transistor and includes a silicon substrate 11 on which a p-type well 11P is formed. The p-type well 11P includes a source region 11S and a drain region 11D that are n-doped. The Dt-MOS transistor 10 also includes a gate insulating film 12 formed on a channel region 11C between the source region 11S and the drain region 11D and a gate electrode 13 formed on the silicon substrate 11 via the gate insulating film 12. The gate electrode 13 includes, for example, n-type polysilicon.
The gate electrode 13 is electrically connected to the p-type well 11P, i.e., a body. Accordingly, a signal voltage applied to the gate electrode 13 is also applied to the body 11P. With this configuration, the signal voltage causes a decrease in the threshold voltage of the Dt-MOS transistor 10 and as the signal voltage increases, the operating characteristics of the Dt-MOS transistor 10 gradually come close to the operating characteristics of a MOS transistor with a low threshold voltage. In this case, the Dt-MOS transistor 10 is turned on with a low signal voltage.
Meanwhile, when the signal voltage is low, i.e., equal or close to 0 V, the electric potential of the body 11P becomes equal or close to 0 V and the operating characteristics of the Dt-MOS transistor 10 come close to the operating characteristics of a MOS transistor with a high threshold voltage. In this case, the threshold voltage of the Dt-MOS transistor 10 is similar to a high threshold voltage of a typical n-channel MOS transistor, and the off-current and the off-leakage current of the Dt-MOS transistor 10 are low as illustrated in FIG. 2.
With the Dt-MOS transistor 10 as described above, since a junction region 11J (surrounded by a dotted line in FIG. 1) between the source region 11S and the body 11P is forward-biased, it is not possible to apply a high supply voltage between the source region 11S and the drain region 11D. When a silicon substrate is used as in the Dt-MOS transistor 10, it is necessary to set the supply voltage at 0.7 V or lower that corresponds to the built-in potential of the silicon pn-junction.
The above descriptions also apply to a p-channel MOS transistor where “p-type” and “n-type” in the Dt-MOS transistor 10 are reversed.
[Patent document 1] Japanese Laid-Open Patent Publication No. 2006-49784
[Patent document 2] Japanese Laid-Open Patent Publication No. 2000-114399
[Non-patent document 1] Assaderaaghi, F. et al., IEEE Electron Device Lett. 15, pp. 510-(1994)
When a Dt-MOS transistor as described above is formed on a typical silicon substrate (hereafter called a silicon bulk substrate) that is cut out from a single-crystal silicon ingot, the leakage current from the source or the drain tends to increase. Also in this case, the junction capacitance between the body and the source region or the drain region may increase and the operation speed of the Dt-MOS transistor may be reduced due to the influence of the time constant. For these reasons, a Dt-MOS transistor is typically formed on a silicon-on-insulator (SOI) substrate (see, for example, non-patent document 1). The operating characteristics in FIG. 2 are obtained using a Dt-MOS transistor formed on a SOI substrate as described in non-patent document 1.
However, in a semiconductor integrated circuit such as a System On Chip (SoC) where a system is implemented on one substrate, transistors other than dynamic threshold transistors such as Dt-MOS transistors are also integrated on the same substrate. Such transistors may include input/output transistors and analog transistors that are not designed to use dynamic thresholds.
Here, with a Dt-MOS transistor, as is apparent from FIG. 1, the same signal applied to the gate electrode is also applied to the channel region directly below the gate electrode. Therefore, when Dt-MOS transistors are integrated on one silicon substrate, the Dt-MOS transistors may interfere with each other or with other transistors.
To prevent such interference, one well may be provided for each transistor and adjacent wells may be electrically separated from each other by a well with an opposite conductivity type. However, this configuration greatly increases the area occupied by the Dt-MOS transistors on the silicon substrate.
FIG. 3 illustrates an exemplary semiconductor structure where two Dt-MOS transistors with the configuration illustrated in FIG. 1 are formed adjacent to each other on one silicon substrate 11.
In FIG. 3, two p-type wells 11P1 and 11P2 are formed in a deep n-type well 11N that is formed in the silicon substrate 11. The Dt-MOS transistors are n-channel Dt-MOS transistors and are formed in the corresponding p-type wells 11P1 and 11P2. The p-type wells 11P1 and 11P2 are separated from each other by an n-type well 11n having a width B and extending upward from the n-type well 11N. A shallow trench isolation (STI) region 11I is formed on the silicon substrate to prevent short circuit of the n-type well 11n and an n-type source region 11S and/or an n-type drain region 11D. The STI region 11I is wider than the n-type well 11n and is deeper than the n-type source region 11S and the n-type drain region 11D.
This configuration may prevent the interference between the n-channel Dt-MOS transistors, but increases the area of the semiconductor structure by the width B of the n-type well 11n separating the p-type wells 11P1 and 11P2.
The width B of the n-type well 11n is determined according to design rules employed and taking into account the breakdown voltage of a pn junction to be formed and an error in the size or the position of an ion implantation mask, and therefore cannot be changed freely. When, for example, the width B is set at 0.5 μm, even if the area of gate electrodes 13 is considered, the area of the semiconductor structure becomes almost two times greater than a case where Dt-MOS transistors are not used, i.e., where the drain region 11D in the p-type well 11P1 is adjacent to the source region 11S in the p-type well 11P2.